Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow is hardware description language (HDL) compilation. HDL compilation involves performing synthesis, placement, routing, and timing analysis of the system on the target device.
Static timing analysis is one approach that may be used to analyze timing of a system on a target device where an expected timing of a digital circuit is computed without requiring the simulation of the full circuit. Static timing analysis may be performed for more than one set of conditions in order to qualify a design across many conditions. If the design operates at each extreme condition, then under the assumption of monatomic behavior, the design should also be qualified for all intermediate points.